VERSION:1.00.00;	DATE:11/19/2025 5:23:42 PM;	TEST ENVIRONMENT:Customer Test;	TEST COVERAGE:Full;	LOOP TYPE:BY COUNT;	LOOP COUNT:1;	VERBOSITY:All
LOOP NO;SLOT:VP NAME;		TESTTYPE NAME;	CHANNEL(S);	RESULT;	FRU;	DIAGNOSTIC;	TIME LAST TESTED
1;	ComputerIO;	PCIT(TCIT)|FPGA Version;	;	Pass;	;	;	11/19/2025 17:23:54
1;	ComputerIO;	PCIT(TCIT)|Registers;	;	Pass;	;	;	11/19/2025 17:23:54
1;	ComputerIO;	PCIT(TCIT)|RetrigTimers;	;	Pass;	;	;	11/19/2025 17:23:54
1;	ComputerIO;	PCIT(TCIT)|FreeTimer;	;	Pass;	;	;	11/19/2025 17:23:54
1;	ComputerIO;	PCIT(TCIT)|Bus PIO Test;	;	Pass;	;	;	11/19/2025 17:23:54
1;	ComputerIO;	JagBus(TCIJ)|FPGA Version;	;	Pass;	;	;	11/19/2025 17:23:54
1;	ComputerIO;	JagBus(TCIJ)|Bus PIO Test;	;	Pass;	;	;	11/19/2025 17:23:54
1;	ComputerIO;	JagBus(TCIJ)|Basic DMA ReadWrite test;	;	Pass;	;	;	11/19/2025 17:23:54
1;	ComputerIO;	JagBus(TCIJ)|Full DMA Test;	;	Pass;	;	;	11/19/2025 17:23:54
1;	SMC;	Configuration;	SMC System Node;	Pass;	;	;	11/19/2025 17:23:54
1;	SMC;	Status;	24:SupportBoard;	Pass;	;	;	11/19/2025 17:23:54
1;	SMC;	Status;	25:SupportBoard;	Pass;	;	;	11/19/2025 17:23:54
1;	SMC;	Status;	SMC CDU & PSU;	Pass;	;	;	11/19/2025 17:23:54
1;	SMC;	Status;	SMC Support Cabinet;	Pass;	;	;	11/19/2025 17:23:54
1;	SMC;	Status;	SMC System Node;	Pass;	;	;	11/19/2025 17:23:54
1;	SMC;	Revisions;	24:SupportBoard;	Pass;	;	;	11/19/2025 17:23:55
1;	SMC;	Revisions;	25:SupportBoard;	Pass;	;	;	11/19/2025 17:23:55
1;	SMC;	Revisions;	SMC CDU & PSU;	Pass;	;	;	11/19/2025 17:23:55
1;	SMC;	Revisions;	SMC Support Cabinet;	Pass;	;	;	11/19/2025 17:23:55
1;	SMC;	Revisions;	SMC System Node;	Pass;	;	;	11/19/2025 17:23:55
1;	SMC;	Communications;	SMC Support Cabinet;	Pass;	;	;	11/19/2025 17:23:55
1;	SMC;	Calibrate;	SMC Support Cabinet;	Pass;	;	;	11/19/2025 17:23:55
1;	SMC;	RAM;	SMC Support Cabinet;	Pass;	;	;	11/19/2025 17:23:55
1;	SMC;	RAM;	SMC System Node;	Pass;	;	;	11/19/2025 17:23:55
1;	SMC;	Echo;	SMC Support Cabinet;	Pass;	;	;	11/19/2025 17:23:55
1;	SMC;	Echo;	SMC System Node;	Pass;	;	;	11/19/2025 17:23:55
1;	SMC;	Flash;	SMC System Node;	Pass;	;	;	11/19/2025 17:23:55
1;	SMC;	Monitor;	24:SupportBoard;	Pass;	;	;	11/19/2025 17:23:55
1;	SMC;	Monitor;	25:SupportBoard;	Pass;	;	;	11/19/2025 17:23:55
1;	SMC;	Monitor;	SMC Support Cabinet;	Pass;	;	;	11/19/2025 17:23:55
1;	24.0:SupportBoard;	Databus|DB Fanout;	;	Pass;	;	;	11/19/2025 17:23:58
1;	25.0:SupportBoard;	Databus|DB Fanout;	;	Pass;	;	;	11/19/2025 17:23:58
1;	24.0:SupportBoard;	Databus|Fargo Registers;	;	Pass;	;	;	11/19/2025 17:23:58
1;	25.0:SupportBoard;	Databus|Fargo Registers;	;	Pass;	;	;	11/19/2025 17:23:58
1;	24.0:SupportBoard;	Databus|Pik Memory;	;	Pass;	;	;	11/19/2025 17:23:58
1;	25.0:SupportBoard;	Databus|Pik Memory;	;	Pass;	;	;	11/19/2025 17:23:58
1;	24.0:SupportBoard;	Databus|IK Memories;	;	Pass;	;	;	11/19/2025 17:23:59
1;	25.0:SupportBoard;	Databus|IK Memories;	;	Pass;	;	;	11/19/2025 17:23:59
1;	24.0:SupportBoard;	Databus|Ik Enables;	;	Pass;	;	;	11/19/2025 17:23:59
1;	25.0:SupportBoard;	Databus|Ik Enables;	;	Pass;	;	;	11/19/2025 17:23:59
1;	24.0:SupportBoard;	Databus|Fargo Slot Uniqueness;	;	Pass;	;	;	11/19/2025 17:23:59
1;	25.0:SupportBoard;	Databus|Fargo Slot Uniqueness;	;	Pass;	;	;	11/19/2025 17:23:59
1;	24.0:SupportBoard;	Databus|Fargo Wait Memories;	;	Pass;	;	;	11/19/2025 17:23:59
1;	25.0:SupportBoard;	Databus|Fargo Wait Memories;	;	Pass;	;	;	11/19/2025 17:23:59
1;	24.0:SupportBoard;	Databus|DMA;	;	Pass;	;	;	11/19/2025 17:24:00
1;	25.0:SupportBoard;	Databus|DMA;	;	Pass;	;	;	11/19/2025 17:24:00
1;	24.0:SupportBoard;	Databus|CTRB Enable;	;	Pass;	;	;	11/19/2025 17:24:00
1;	25.0:SupportBoard;	Databus|CTRB Enable;	;	Pass;	;	;	11/19/2025 17:24:00
1;	24.0:SupportBoard;	Databus|Funnel Enables;	;	Pass;	;	;	11/19/2025 17:24:00
1;	25.0:SupportBoard;	Databus|Funnel Enables;	;	Pass;	;	;	11/19/2025 17:24:00
1;	24.0:SupportBoard;	FPGA Versions;	;	Pass;	;	;	11/19/2025 17:24:00
1;	25.0:SupportBoard;	FPGA Versions;	;	Pass;	;	;	11/19/2025 17:24:00
1;	24.0:SupportBoard;	Register & Memory|Newport0 RegMem;	;	Pass;	;	;	11/19/2025 17:24:00
1;	25.0:SupportBoard;	Register & Memory|Newport0 RegMem;	;	NotApplicable;	;	;	11/19/2025 17:24:00
1;	24.0:SupportBoard;	Register & Memory|Newport1 RegMem;	;	Pass;	;	;	11/19/2025 17:24:00
1;	25.0:SupportBoard;	Register & Memory|Newport1 RegMem;	;	NotApplicable;	;	;	11/19/2025 17:24:00
1;	24.0:SupportBoard;	Register & Memory|Soho RegMem;	;	Pass;	;	;	11/19/2025 17:24:01
1;	25.0:SupportBoard;	Register & Memory|Soho RegMem;	;	Pass;	;	;	11/19/2025 17:24:01
1;	24.0:SupportBoard;	Clock|TCAL0|DDS;	;	Pass;	;	;	11/19/2025 17:24:01
1;	25.0:SupportBoard;	Clock|TCAL0|DDS;	;	NotApplicable;	;	;	11/19/2025 17:24:01
1;	24.0:SupportBoard;	Clock|TCAL0|Frequency;	;	Pass;	;	;	11/19/2025 17:24:01
1;	25.0:SupportBoard;	Clock|TCAL0|Frequency;	;	NotApplicable;	;	;	11/19/2025 17:24:01
1;	24.0:SupportBoard;	Clock|TCAL0|Coincidence Counter;	;	Pass;	;	;	11/19/2025 17:24:06
1;	25.0:SupportBoard;	Clock|TCAL0|Coincidence Counter;	;	NotApplicable;	;	;	11/19/2025 17:24:06
1;	24.0:SupportBoard;	Clock|TCAL0|Sequencer;	;	Pass;	;	;	11/19/2025 17:24:07
1;	25.0:SupportBoard;	Clock|TCAL0|Sequencer;	;	NotApplicable;	;	;	11/19/2025 17:24:07
1;	24.0:SupportBoard;	Clock|TCAL0|Toss Jitter;	;	Pass;	;	;	11/19/2025 17:24:07
1;	25.0:SupportBoard;	Clock|TCAL0|Toss Jitter;	;	NotApplicable;	;	;	11/19/2025 17:24:07
1;	24.0:SupportBoard;	Clock|TCAL1|DDS;	;	Pass;	;	;	11/19/2025 17:24:27
1;	25.0:SupportBoard;	Clock|TCAL1|DDS;	;	NotApplicable;	;	;	11/19/2025 17:24:27
1;	24.0:SupportBoard;	Clock|TCAL1|Frequency;	;	Pass;	;	;	11/19/2025 17:24:27
1;	25.0:SupportBoard;	Clock|TCAL1|Frequency;	;	NotApplicable;	;	;	11/19/2025 17:24:27
1;	24.0:SupportBoard;	Clock|TCAL1|Coincidence Counter;	;	Pass;	;	;	11/19/2025 17:24:32
1;	25.0:SupportBoard;	Clock|TCAL1|Coincidence Counter;	;	NotApplicable;	;	;	11/19/2025 17:24:32
1;	24.0:SupportBoard;	Clock|TCAL1|Sequencer;	;	Pass;	;	;	11/19/2025 17:24:32
1;	25.0:SupportBoard;	Clock|TCAL1|Sequencer;	;	NotApplicable;	;	;	11/19/2025 17:24:32
1;	24.0:SupportBoard;	Clock|TCAL1|Toss Jitter;	;	Pass;	;	;	11/19/2025 17:24:33
1;	25.0:SupportBoard;	Clock|TCAL1|Toss Jitter;	;	NotApplicable;	;	;	11/19/2025 17:24:33
1;	24.0:SupportBoard;	Misc. Functions|Dig Gnd Sense;	;	Pass;	;	;	11/19/2025 17:24:52
1;	25.0:SupportBoard;	Misc. Functions|Dig Gnd Sense;	;	NotApplicable;	;	;	11/19/2025 17:24:52
1;	24.0:SupportBoard;	Misc. Functions|Lv Dc Cal Ref;	;	Pass;	;	;	11/19/2025 17:24:52
1;	25.0:SupportBoard;	Misc. Functions|Lv Dc Cal Ref;	;	NotApplicable;	;	;	11/19/2025 17:24:52
1;	24.0:SupportBoard;	Misc. Functions|Dac Cal Ref;	;	Pass;	;	;	11/19/2025 17:24:52
1;	25.0:SupportBoard;	Misc. Functions|Dac Cal Ref;	;	NotApplicable;	;	;	11/19/2025 17:24:52
1;	24.0:SupportBoard;	Misc. Functions|Utility Bits;	;	Pass;	;	;	11/19/2025 17:24:52
1;	25.0:SupportBoard;	Misc. Functions|Utility Bits;	;	NotApplicable;	;	;	11/19/2025 17:24:52
1;	24.0:SupportBoard;	DcCalTest;	;	Pass;	;	;	11/19/2025 17:24:52
1;	25.0:SupportBoard;	DcCalTest;	;	NotApplicable;	;	;	11/19/2025 17:24:52
1;	24.0:SupportBoard;	TimingCalLevels;	;	Pass;	;	;	11/19/2025 17:25:00
1;	25.0:SupportBoard;	TimingCalLevels;	;	NotApplicable;	;	;	11/19/2025 17:25:00
1;	24.0:SupportBoard;	TDR Continuity;	;	Pass;	;	;	11/19/2025 17:25:14
1;	25.0:SupportBoard;	TDR Continuity;	;	Pass;	;	;	11/19/2025 17:25:14
1;	62.0:DistributionBoard;	Databus|DB Fanout;	;	Pass;	;	;	11/19/2025 17:25:17
1;	63.0:DistributionBoard;	Databus|DB Fanout;	;	Pass;	;	;	11/19/2025 17:25:17
1;	62.0:DistributionBoard;	Databus|DMA;	;	Pass;	;	;	11/19/2025 17:25:17
1;	63.0:DistributionBoard;	Databus|DMA;	;	Pass;	;	;	11/19/2025 17:25:17
1;	62.0:DistributionBoard;	Databus|Ik Enables;	;	Pass;	;	;	11/19/2025 17:25:18
1;	63.0:DistributionBoard;	Databus|Ik Enables;	;	Pass;	;	;	11/19/2025 17:25:18
1;	62.0:DistributionBoard;	Databus|Fargo Slot Uniqueness;	;	Pass;	;	;	11/19/2025 17:25:18
1;	63.0:DistributionBoard;	Databus|Fargo Slot Uniqueness;	;	Pass;	;	;	11/19/2025 17:25:18
1;	62.0:DistributionBoard;	Databus|Fargo Channel Uniqueness;	;	Pass;	;	;	11/19/2025 17:25:18
1;	63.0:DistributionBoard;	Databus|Fargo Channel Uniqueness;	;	Pass;	;	;	11/19/2025 17:25:18
1;	62.0:DistributionBoard;	Databus|CTRB Enable;	;	Pass;	;	;	11/19/2025 17:25:18
1;	63.0:DistributionBoard;	Databus|CTRB Enable;	;	Pass;	;	;	11/19/2025 17:25:18
1;	62.0:DistributionBoard;	Databus|Funnel Enables;	;	Pass;	;	;	11/19/2025 17:25:18
1;	63.0:DistributionBoard;	Databus|Funnel Enables;	;	Pass;	;	;	11/19/2025 17:25:18
1;	62.0:DistributionBoard;	FPGA Versions;	;	Pass;	;	;	11/19/2025 17:25:19
1;	63.0:DistributionBoard;	FPGA Versions;	;	Pass;	;	;	11/19/2025 17:25:19
1;	62.0:DistributionBoard;	Register & Memory|Fargo Wait Memories;	;	Pass;	;	;	11/19/2025 17:25:19
1;	63.0:DistributionBoard;	Register & Memory|Fargo Wait Memories;	;	Pass;	;	;	11/19/2025 17:25:19
1;	62.0:DistributionBoard;	Register & Memory|Fargo Registers;	15..31;	Pass;	;	;	11/19/2025 17:25:19
1;	63.0:DistributionBoard;	Register & Memory|Fargo Registers;	15..31;	Pass;	;	;	11/19/2025 17:25:19
1;	62.0:DistributionBoard;	Register & Memory|IK Memories;	;	Pass;	;	;	11/19/2025 17:25:19
1;	63.0:DistributionBoard;	Register & Memory|IK Memories;	;	Pass;	;	;	11/19/2025 17:25:19
1;	62.0:DistributionBoard;	Register & Memory|Pik Memory;	;	Pass;	;	;	11/19/2025 17:25:20
1;	63.0:DistributionBoard;	Register & Memory|Pik Memory;	;	Pass;	;	;	11/19/2025 17:25:20
1;	62.0:DistributionBoard;	Register & Memory|Coney Registers;	;	Pass;	;	;	11/19/2025 17:25:21
1;	63.0:DistributionBoard;	Register & Memory|Coney Registers;	;	Pass;	;	;	11/19/2025 17:25:21
1;	62.0:DistributionBoard;	Register & Memory|L2R;	;	Pass;	;	;	11/19/2025 17:25:21
1;	63.0:DistributionBoard;	Register & Memory|L2R;	;	Pass;	;	;	11/19/2025 17:25:21
1;	62.0:DistributionBoard;	ISL|Router Loopback;	;	Pass;	;	;	11/19/2025 17:25:22
1;	63.0:DistributionBoard;	ISL|Router Loopback;	;	Pass;	;	;	11/19/2025 17:25:22
1;	62.0:DistributionBoard;	ISL|Router Filter;	;	Pass;	;	;	11/19/2025 17:25:22
1;	63.0:DistributionBoard;	ISL|Router Filter;	;	Pass;	;	;	11/19/2025 17:25:22
1;	62.0:DistributionBoard;	Move Link|L2R Port Test;	;	Pass;	;	;	11/19/2025 17:25:27
1;	63.0:DistributionBoard;	Move Link|L2R Port Test;	;	Pass;	;	;	11/19/2025 17:25:27
1;	62.0:DistributionBoard;	Move Link|X4 Cross Hemi;	;	Pass;	;	;	11/19/2025 17:25:27
1;	63.0:DistributionBoard;	Move Link|X4 Cross Hemi;	;	Pass;	;	;	11/19/2025 17:25:27
1;	66.0:VirtualDSPBrd;	Host to DSP Link;	;	Pass;	;	;	11/19/2025 17:25:29
1;	66.0:VirtualDSPBrd;	BIOSChecker;	;	Pass;	;	;	11/19/2025 17:26:10